`timescale 1 ns / 1 ps
/*------------------- include --------------------*/

/*---------------------------------------------*/

`define CLOCK_FREQ_MHz 50.0   //系统主频 MHz

module tb; 

reg clk ; 

reg rst_n;          //复位信号


//生成时钟
parameter NCLK = 1000/`CLOCK_FREQ_MHz; 
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end

/*----------------------------- 模块 ------------------------------*/
reg signed [15:0] speed = 0 ;

cpsm_io u_cpsm_io(
    .clk( clk ),
    .rst_n(rst_n) , 
    .gpio0()
);




initial begin
    $display(" -------- cpsm_io sim ----------");
    rst_n = 0;
    repeat(2) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(50000) @(posedge clk) ;

    $display("%d ns:done",$time);
	$dumpflush;
	$finish;
	$stop;	
end

endmodule
